Datasheet for AD9278:
- Manufacturer Part Number : AD9278
- Manufacturer : AD
- Description : Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator
- Series : AD9278
- Reference Price : USD 38.4
- Our Price : We have a better price, contact us by email
- Product Type : High Speed A/D Converters >10 MSPS
- Function : Standard High Speed A/D Converters >20 MSPS
- Current Suggest : Recommended for New Designs
- Status : Production
- RoHS Status: -
- Voltage: -
- Feature: -
- Package Case: -
- Temperature Range: -
- Packing: Reel/Tray/Tube
- Standard Packing Quantity: -
- Country of Origin: -
- Other Part Number : AD9278
- Shipping methods : DHL FEDEX UPS TNT
- Delivery Time : Ship within 1 day.
- Manufacturer Production time : 6-8 weeks (Normally have stocks)
- Weight : 0.001KG
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- Low power: 88 mW per channel, TGC mode, 40 MSPS;
32 mW per channel, CW mode - 10 mm × 10 mm, 144-ball CSP-BGA
- TGC channel input-referred noise: 1.3 nV/√Hz, max gain
- Flexible power-down modes
- Fast recovery from low power standby mode: <2 μs
- Overload recovery: <10 ns
- Input-referred noise: 1.25 nV/√Hz, gain = 21.3 dB
- Programmable gain: 15.6 dB/17.9 dB/21.3 dB
- 0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p
- Dual-mode active input impedance matching
- Bandwidth (BW): >50 MHz
- Attenuator range: −45 dB to 0 dB
- Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
- Linear-in-dB gain control
- Programmable second-order LPF from 8 MHz to 18 MHz
- Programmable HPF
- SNR: 70 dB, 12 bits up to 65 MSPS
- Serial LVDS (ANSI-644, low power/reduced signal)
- Individual programmable phase rotation
- Output dynamic range per channel: >158 dBc/√Hz
- Output-referred SNR: 153 dBc/√Hz, 1 kHz offset, −3dBFS
Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 51 dB, and an ADC with a conversion rate of up to 65 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 1.3 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 1.3 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 88 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has inde-pendently programmable phase rotation through the SPI with 16 phase settings.
The AD9278 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.
Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler opera-tion, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo-random patterns, and custom user-defined test patterns entered via the serial port interface.
Fabricated in an advanced BiCMOS process, the AD9278 is available in a 10 mm × 10 mm, RoHS compliant, 144-lead BGA. It is specified over the industrial temperature range of −40°C to +85°C.
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.