Datasheet for AD9656:
- Manufacturer Part Number : AD9656
- Manufacturer : AD
- Description : Quad, 16-Bit, 125 MSPS JESD204B 1.8 V Analog-to-Digital Converter
- Series : AD9656
- Reference Price : USD 206.616
- Our Price : We have a better price, contact us by email
- Product Type : High Speed A/D Converters >10 MSPS
- Function : Standard High Speed A/D Converters >20 MSPS
- Current Suggest : Recommended for New Designs
- Status : Production
- RoHS Status: -
- Voltage: -
- Feature: -
- Package Case: -
- Temperature Range: -
- Packing: Reel/Tray/Tube
- Standard Packing Quantity: -
- Country of Origin: -
- Other Part Number : AD9656
- Shipping methods : DHL FEDEX UPS TNT
- Delivery Time : Ship within 1 day.
- Manufacturer Production time : 6-8 weeks (Normally have stocks)
- Weight : 0.001KG
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The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digitalconverter (ADC) with an on-chip sample and hold circuitdesigned for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS andis optimized for outstanding dynamic performance and lowpower in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performanceoperation. An external reference or driver components are notrequired for many applications.
Individual channel power-down is supported and typically consumes less than 14 mW when all channels are disabled. TheADC contains several features designed to maximize flexibilityand minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The availabledigital test patterns include built-in deterministic and pseudo-random patterns, along with custom user-defined test patternsentered via the serial port interface (SPI).
The AD9656 is available in an RoHS compliant, nonmagnetic, 56-lead LFCSP. It is specified over the −40°C to +85°Cindustrial temperature range.
Product Highlights
- It has a small footprint. Four ADCs are contained in a small, 8 mm × 8 mm package.
- An on-chip phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
- The configurable JESD204B output block supports up to 8.0 Gbps per lane.
- JESD204B output block supports one, two, and four lane configurations.
- Low power of 198 mW per channel at 125 MSPS, two lanes.
- The SPI control offers a wide range of flexible features to meet specific system requirements.
Applications
- Medical imaging
- High speed imaging
- Quadrature radio receivers
- Diversity radio receivers
- Portable test equipment
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
