The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.

The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.

Applications

• Communications
• Diversity multi-band, multi-mode digital receivers
  3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE
• General-purpose software radios
• Ultrawideband satellite receiver
• Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
• Radar
• Digital oscilloscopes
• High speed data acquisition systems
• DOCSIS CMTS upstream receive paths
• HFC digital reverse path receivers

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.