The 10 clock outputs of the AD9542 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.

The AD9542 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.

Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.

Applications

• SyncE jitter cleanup and synchronization
• Optical transport networks (OTN), SDH, and macro and small cell base stations
• OTN mapping/demapping with jitter cleaning
• Small base station clocking, including baseband and radio
• Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
• JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
• Cable infrastructures
• Carrier Ethernet

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.