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Manufacturer / Brand: AD
Details: IEEE1588 Version 2 and 1 pps Synchronizer and Adaptive Clock Translator IC
Series: AD9545
Quantity Available: Over 40150 pieces

Datasheet for AD9545BCPZ-REEL7:

AD9545BCPZ-REEL7 datasheet
Price for AD9545BCPZ-REEL7
Product Parameters
  • Manufacturer Part Number : AD9545BCPZ-REEL7
  • Manufacturer : AD
  • Description : IEEE1588 Version 2 and 1 pps Synchronizer and Adaptive Clock Translator IC
  • Series : AD9545
  • Reference Price : USD 11.968
  • Our Price : We have a better price, contact us by email
  • Product Type : Clock Generation & Distribution
  • Function : Clock Synchronization
  • Current Suggest : Recommended for New Designs
  • Status : Production
  • ROHS Status : ROHS Compliant (Lead Free)
  • Package Type : 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP)
  • Pins : 48
  • MFG Package Case : CP-48-13
  • Part Type : REEL
  • Standard Packing Type : Reel
  • Standard Packing Quantity : 750
  • Working Temperature : -40 to 85C
  • Other Part Number : AD9545BCPZ-REEL7
  • Shipping methods : DHL FEDEX UPS TNT
  • Delivery Time : Ship within 1 day.
  • Manufacturer Production time : 6-8 weeks (Normally have stocks)
  • Weight : 0.001KG

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Features and Benefits of AD9545BCPZ-REEL7
  • Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy references
  • Complies with ITU-T G.8262 and Telcordia GR-253
  • Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2
  • Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 10−8)
  • Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
  • Programmable digital loop filter bandwidth: 10−4Hz to 1850Hz
  • 2 independent, programmable auxiliary NCOs (1 Hz to 65,535 Hz, resolution < 1.37 × 10−12 Hz), suitable for IEEE 1588 Version 2 servo feedback in PTP applications
  • Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
  • Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
  • 5 pairs of clock output pins with each pair usable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
  • 2 differential or 4 single-ended input references
  • Crosspoint mux interconnects reference inputs to PLLs
  • Supports embedded (modulated) input/output clock signals
  • Fast DPLL locking modes
  • Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
  • External EEPROM support for autonomous initialization
  • Single 1.8 V power supply operation with internal regulation
  • Built in temperature monitor and alarm and temperature compensation for enhanced zero delay performance
Product Detailed Description for AD9545BCPZ-REEL7

The AD9545 supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2.

The 10 clock outputs of the AD9545 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.

The AD9545 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.

Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.

Applications

  • Global positioning system (GPS), PTP (IEEE 1588), and synchronous Ethernet (SyncE) jitter cleanup and synchronization
  • Optical transport networks (OTN), synchronous digital hierarchy (SDH), and macro and small cell base stations
  • Small base station clocking, including baseband and radio
  • Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
  • JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
  • Cable infrastructures
  • Carrier Ethernet
Lifecycle information of AD9545BCPZ-REEL7

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

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