The AD9558 is a low loop bandwidth clock multiplier that providesjitter cleanup and synchronization for many systems, includingsynchronous optical networks (OTN/SONET/SDH). The AD9558generates an output clock synchronized to up to four external inputreferences. The digital phase-locked loop (PLL) allows reductionof input time jitter or phase noise associated with the externalreferences. The digitally controlled loop and holdover circuitryof the AD9558 continuously generates a low jitter output clockeven when all reference inputs have failed.

The AD9558 operates over an industrial temperature range of−40°C to +85°C. If a smaller package is required, refer to theAD9557 for the two-input/two-output version of the same device.

Applications

• Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping
• Cleanup of reference clock jitter
• SONET/SDH/OTN clocks up to 100 Gbps, including FEC
• Stratum 3 holdover, jitter cleanup, and phase transient control
• Wireless base station controllers
• Cable infrastructure
• Data communications

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.