The ADF4151 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external voltage controlled oscillator (VCO), loop filter, and external reference frequency.

The ADF4151 is used with external VCO parts and is footprint and software compatible with the ADF4350. The part consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider [N = (INT + (FRAC/MOD))]. The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4151 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.

Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V that can be powered down when not in use.

The ADF4151 is available in a 5 mm × 5 mm package.

Applications

• Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax,
  GSM, PCS, DCS, DECT)
• Test equipment
• Wireless LANs, CATV equipment
• Clock generation

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.