Datasheet for EVAL-SDP-CS1Z:
- Manufacturer Part Number : EVAL-SDP-CS1Z
- Manufacturer : AD
- Description : Low Phase Noise, Fast Settling 6 GHz PLL Frequency Synthesizer IC
- Series : ADF4196
- Reference Price : USD 0
- Our Price : We have a better price, contact us by email
- Product Type : Phase Locked Loop (PLL) Synthesizers
- Function : Fractional-N PLL
- Current Suggest : Recommended for New Designs
- Status : Production
- ROHS Status : ROHS Compliant (Lead Free)
- Package Type : SDP-S Controller Board - Interface to EV-ADF4196SD1Z (also required)
- Pins : -
- MFG Package Case : -
- Part Type : EVAL
- Standard Packing Type : -
- Standard Packing Quantity : -
- Working Temperature : -
- Other Part Number : EVAL-SDP-CS1Z
- Shipping methods : DHL FEDEX UPS TNT
- Delivery Time : Ship within 1 day.
- Manufacturer Production time : 6-8 weeks (Normally have stocks)
- Weight : 0.001KG
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The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture isspecifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes theADF4196 suitable for pulse Doppler radar applications.
The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (Σ-Δ) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.
Applications
- GSM/EDGE base stations
- PHS base stations
- Pulsed Doppler radar
- Instrumentation and test equipment
- Beam-forming/phased array systems
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
