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Manufacturer / Brand: AD
Details: Low Phase Noise, Fast Settling PLL Frequency Synthesizer IC
Series: ADF4193
Quantity Available: Over 7810 pieces

Datasheet for EV-ADF4193SD1Z:

EV-ADF4193SD1Z datasheet
Price for EV-ADF4193SD1Z
Product Parameters
  • Manufacturer Part Number : EV-ADF4193SD1Z
  • Manufacturer : AD
  • Description : Low Phase Noise, Fast Settling PLL Frequency Synthesizer IC
  • Series : ADF4193
  • Reference Price : USD 0
  • Our Price : We have a better price, contact us by email
  • Product Type : Phase Locked Loop (PLL) Synthesizers
  • Function : Fractional-N PLL
  • Current Suggest : Production
  • Status : Contact ADI
  • ROHS Status : ROHS Compliant (Lead Free)
  • Package Type : Evaluation board with 1.8 GHz VCO and loop filter components populated
  • Pins : -
  • MFG Package Case : -
  • Part Type : EVAL
  • Standard Packing Type : -
  • Standard Packing Quantity : -
  • Working Temperature : -
  • Other Part Number : EV-ADF4193SD1Z
  • Shipping methods : DHL FEDEX UPS TNT
  • Delivery Time : Ship within 1 day.
  • Manufacturer Production time : 6-8 weeks (Normally have stocks)
  • Weight : 0.001KG

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Features and Benefits of EV-ADF4193SD1Z
Product Detailed Description for EV-ADF4193SD1Z

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).

The Σ-Δ-based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures.

Applications

  • GSM/EDGE base stations
  • PHS base stations
  • Instrumentation and test equipment
Lifecycle information of EV-ADF4193SD1Z

At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.

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