Datasheet for ADRF5545A-EVALZ:
- Manufacturer Part Number : ADRF5545A-EVALZ
- Manufacturer : AD
- Description : Dual-Channel, 2.4 GHz to 4.2 GHz Receiver Front End IC
- Series : ADRF5545A
- Reference Price : USD 0
- Our Price : We have a better price, contact us by email
- Product Type : RF Integrated Transmitters, Receivers, & Transceivers
- Function : RF Front End ICs
- Current Suggest : Recommended for New Designs
- Status : Production
- ROHS Status : ROHS Compliant (Lead Free)
- Package Type : Evaluation Board
- Pins : -
- MFG Package Case : -
- Part Type : EVAL
- Standard Packing Type : -
- Standard Packing Quantity : -
- Working Temperature : -
- Other Part Number : ADRF5545A-EVALZ
- Shipping methods : DHL FEDEX UPS TNT
- Delivery Time : Ship within 1 day.
- Manufacturer Production time : 6-8 weeks (Normally have stocks)
- Weight : 0.001KG
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- Integrated dual-channel RF front end
- 2-stage LNA and high power SPDT switch
- On-chip bias and matching
- Single supply operation
- Gain
- High gain mode: 32 dB typical at 3.6 GHz
- Low gain mode: 16 dB typical at 3.6 GHz
- Low noise figure
- High gain mode: 1.45 dB typical at 3.6 GHz
- Low gain mode: 1.45 dB typical at 3.6 GHz
- High isolation
- RXOUT-CHA and RXOUT-CHB: 47 dB typical
- TERM-CHA and TERM-CHB: 52 dB typical
- Low insertion loss: 0.65 dB typical at 3.6 GHz
- High power handling at TCASE = 105°C
- Full lifetime
- LTE average power (9 dB PAR): 40 dBm
- Single event (<10 sec operation)
- LTE average power (9 dB PAR): 43 dBm
- Full lifetime
- High OIP3: 32 dBm typical
- Power-down mode and low gain mode for LNA
- Low supply current
- High gain mode: 86 mA typical at 5 V
- Low gain mode: 36 mA typical at 5 V
- Power-down mode: 12 mA typical at 5 V
- Positive logic control
- 6 mm × 6 mm, 40-lead LFCSP package
The ADRF5545A is a dual-channel, integrated radio frequency (RF), front-end multichip module designed for time division duplexing (TDD) applications that operates from 2.4 GHz to 4.2 GHz. The ADRF5545A is configured in dual channels with a cascading two-stage low noise amplifier (LNA) and a high power silicon single-pole, double-throw (SPDT) switch.
In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure (NF) of 1.45 dB and a high gain of 32 dB at 3.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 16 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.
In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.65 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (<10 sec) LNA protection operation.
The device comes in an RoHS compliant, compact, 6 mm × 6 mm, 40-lead LFCSP package.
Applications
- Wireless infrastructure
- TDD massive multiple input and multiple output and active antenna systems
- TDD-based communication systems
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
