Datasheet for ADRF5547-EVALZ:
- Manufacturer Part Number : ADRF5547-EVALZ
- Manufacturer : AD
- Description : Dual-Channel, 3.7 GHz to 5.3 GHz, Receiver Front End IC
- Series : ADRF5547
- Reference Price : USD 0
- Our Price : We have a better price, contact us by email
- Product Type : RF Integrated Transmitters, Receivers, & Transceivers
- Function : RF Front End ICs
- Current Suggest : Recommended for New Designs
- Status : Production
- ROHS Status : ROHS Compliant (Lead Free)
- Package Type : Evaluation Board
- Pins : -
- MFG Package Case : -
- Part Type : EVAL
- Standard Packing Type : -
- Standard Packing Quantity : -
- Working Temperature : -
- Other Part Number : ADRF5547-EVALZ
- Shipping methods : DHL FEDEX UPS TNT
- Delivery Time : Ship within 1 day.
- Manufacturer Production time : 6-8 weeks (Normally have stocks)
- Weight : 0.001KG
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- Integrated dual-channel RF front end
- 2-stage LNA and high power SPDT switch
- On-chip bias and matching
- Single supply operation
- Gain
- High gain mode: 33 dB typical at 4.6 GHz
- Low gain mode: 18 dB typical at 4.6 GHz
- Low noise figure
- High gain mode: 1.6 dB typical at 4.6 GHz
- Low gain mode: 1.6 dB typical at 4.6 GHz
- High channel to channel isolation
- Between RxOUT-ChA and RxOUT-ChB: 45 dB typical
- Between TERM-ChA and TERM-ChB: 53 dB typical
- Low insertion loss: 0.5 dB typical at 4.6 GHz
- High power handling at TCASE = 105°C
- Full lifetime
- LTE average power (9 dB PAR): 40 dBm
- Single event (<10 sec operation)
- LTE average power (9 dB PAR): 43 dBm
- High OIP3: 31 dBm typical
- Power-down mode and low gain mode for LNA
- Low supply current
- High gain mode: 86 mA typical at 5 V
- Low gain mode: 36 mA typical at 5 V
- Power-down mode: 12 mA typical at 5 V
- Positive logic control
- 40-lead, 6 mm × 6 mm LFCSP
The ADRF5547 is a dual-channel, integrated RF, front end multichip module designed for time division duplexing (TDD) applications that operates from 3.7 GHz to 5.3 GHz. The ADRF5547 is configured in dual channels with a cascading twostage low noise amplifier (LNA) and a high power silicon, single-pole, double-throw (SPDT) switch.
In high gain mode, the cascaded, two-stage LNA and switch offer a low noise figure of 1.6 dB and high gain of 33 dB at 4.6 GHz with an output third order intercept point (OIP3) of 31 dBm (typical).
In low gain mode, one stage of the two-stage LNAs is in bypass, providing 18 dB gain at lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.
In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.50 dB and handles long term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (<10 sec) LNA protection operation.
The device comes in an RoHS compliant, compact, 40-lead, 6 mm × 6 mm LFCSP.
Applications
- Wireless infrastructure
- TDD Massive Multiple input and Multiple Output (MIMO) and Active Antenna Systems
- TDD-based Communication Systems
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
