Datasheet for ADRF6604:
- Manufacturer Part Number : ADRF6604
- Manufacturer : AD
- Description : 1200 MHz TO 3600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO
- Series : ADRF6604
- Reference Price : USD 0
- Our Price : We have a better price, contact us by email
- Product Type : RF Integrated Transmitters, Receivers, & Transceivers
- Function : RF Mixers with Integrated LO
- Current Suggest : Not Recommended for New Designs
- Status : Last Time Buy
- RoHS Status: -
- Voltage: -
- Feature: -
- Package Case: -
- Temperature Range: -
- Packing: Reel/Tray/Tube
- Standard Packing Quantity: -
- Country of Origin: -
- Other Part Number : ADRF6604
- Shipping methods : DHL FEDEX UPS TNT
- Delivery Time : Ship within 1 day.
- Manufacturer Production time : 6-8 weeks (Normally have stocks)
- Weight : 0.001KG
Contact us to check the best price and real time inventory quantity for ADRF6604. If you need any more information about ADRF6604, you can also send us by email. Our email is [email protected], we will reply you in 12 hours.
- Rx mixer with integrated fractional-N PLL
- RF input frequency range: 1200 MHz to 3600 MHz
- Internal LO frequency range:
2500 MHz to 2900 MHz - Input P1dB: 14.5 dBm
- Input IP3: 27.5 dBm
- IIP3 optimization via external pin
- SSB noise figure
IP3SET pin open: 14.3 dB
IP3SET pin at 3.3 V: 15.5 dB - Voltage conversion gain: 6.8 dB
- Matched 200 Ω IF output impedance
- IF 3 dB bandwidth: 500 MHz
- Programmable via 3-wire SPI interface
- 40-lead, 6 mm × 6 mm LFCSP
The ADRF6604 is a high dynamic range active mixer with integrated phase-locked loop (PLL) and voltage controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate a fLO input to the mixer. The reference input can be divided or multiplied and then applied to the PLL phase frequency detector (PFD).
The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter.
The loop filter output is then applied to an integrated VCO. The VCO output at 2 × fLO is applied to an LO divider, as well as to a programmable PLL divider. The programmable PLL divider is controlled by a sigma-delta (Σ-Δ) modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047.
The active mixer converts the single-ended, 50 Ω RF input to a differential, 200 Ω IF output. The IF output can operate up to 500 MHz.
The ADRF6604 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range.
Applications
- Cellular base stations
This designates products ADI does not recommend broadly for new designs.
